Brad Taylor
02-02-2023
Reference Schematics
0.07(02-02-2023)- Initial public release
Introduction
The 16-bit LS181/AS881 TTL Computer is an entirely new, original concept 16-bit microcomputer architecture standard documented on this website that is based off mostly common TTL parts.
As there is a sea of TTL parts to navigate through that have seemingly useless application on the surface level, there is a way to organize together a larger, function-specific group of these chips to build a pretty decent and capable 16-bit computer system, with opportunity for expansion on both the physical front, and architectural as well.
Please note the computer design described in this video is currently just conceptual; it is untested, and intended for educational or entertainment purposes only.
LS181/AS881 TTL Computer Goals
- Use LEDs to show the status of as many internal CPU system lines as possible, mostly for amusement but also for debugging
- Enable a way for users to stop and single-step the CPU
- Use front panel switches to program the computer in a pinch
- Offer efficient multiplication and division instruction slices
- Run at TTL-friendly bus speeds, and offer parallel i/o breakout headers for easy peripheral, rPi and Arduino project access
- Eventually develop a printed circuit board, and supply kits to hobbyists and electronics educators for purchase.
Main Functioning Computer Parts
- 1 megabyte ROM BIOS flash
- 1 to 3 megabytes level 1 cache RAM
- 12 MHz system clock generator and pushbutton debounce clock select jumpers
- 8-element CPU register stack
- 16-function carry generator
- 181/881 32-function arithmetic logic unit
- twin shift registers R7 and B, quad bus multiplexer
- 5-bit flags register
- Address register A
- 74LS612 memory mapper and system boot flip-flop
- boot mode jumpers
- 5-bit direct decode control bus
- 19-bit address bus
- 16-bit data bus
- 8 system expansion headers
- 16 console pushbutton switches
- 4 system control pushbutton switches
- 8 dedicated interrupt request inputs
- Interrupt microprogram and instruction fetch sequencer
- Instruction word register
- Instruction decoders
- 208 console status LEDs
1 Megabyte ROM BIOS Flash
This full-speed 8-bit flash memory is a popular type that is widely available and uses a standard flash sequence interface. The largest size is 512 kilobytes, doubled up to provide a 16-bit bus and up to 1 megabyte of system ROM BIOS.
1 to 3 Megabytes Level 1 Cache RAM
This 55-nanosecond 8-bit RAM runs at the system clock speed and effectively functions as a level one cache. The chips are used in pairs to provide a 16-bit bus to the system; up to 3 megabytes of this level one cache may be installed.
12 MHz System Clock Generator & Pushbutton Debounce Clock Select Jumpers
The clock generator circuit, consisting mostly of a crystal oscillator and clock divider, is the source of both the 12 MHz high-speed system clock, and also the low-frequency debouncing clock for debouncing the console pushbutton switches. The HEF4521 contains a 24-stage divider to reduce the 12 MHz signal down to frequencies suitable for debouncing; 6, 11, 23, and 46 samples a second are possible sample rates, set by a jumper block on the system board.
8-Element CPU Register Stack
The CPU register stack is made up of eight pairs of 74F825 8-bit register chips, consisting of program counter (R0), stack pointer (R1), registers R2 to R6, and an address register (just called “A”). The reason these specific register chips are used in the computer here is because they offer a direct reset, clock enable and 3 output select input lines. Having the 3 output select lines allows up to 8 of these chips to be multiplexed together without the need for any extra decoding logic; this makes them suitable to drive the address bus on the same clock cycle as the instruction decode with minimal added propagation delays. The reset lines are useful for initializing the program counter and other registers to 0 on reset; $0000 is where the reset vector starts in the ROM BIOS.
16-Function Carry Generator
There are special instructions on the processor to inject the status of several system flags as the carry input to the arithmetic logic unit; this allows these flags to be easily used in ALU calculations. Moreover, it is a convenient way to extend the status of these flags into the contents of an entire 16-bit register for parallel masking operations.
74LS181/AS881 Arithmetic Logic Units
These classic TTL ALUs contain not only every possible logic function of 2 terms in its instruction set, but also contain enough arithmetic modes to be useful for add, subtract, increment, decrement, left shift and rotate operations, and carry-in operations. The AS881 ALUs contain additional circuitry for calculating the minus one result of a logic operation through the carry, and allows the carry in to be used for cascading multi-word tests for minus one.
Zero Detect
Unfortunately, the LS181 / AS881 ALU design is optimized for processing negative logic. When using positive logic, the equals output on the chip does not actually detect a zero result from the function, but rather minus 1. To provide a proper zero result detection flag to the system we are using a 74ALS677 chip; a versatile address decoder chip configured to provide the zero result detection for the flags.
Twin Shift Registers: B + R7
In order to implement an efficient way of doing iterative multiplication and division operations, the system also provides an additional 2 registers, “B” and R7 which can be shifted left or right, and can also be cascaded for multi-word shifts.
Using the ALU in tandem with the double shift instructions allows up to 48 bits to be shifted in one instruction.
4-Input Data Bus Selector
This 4-input data multiplexer provides the pathway switching required to implement the most useful instructions for the computer.
5-bit Flags Register
The system has a 5-bit flags register: Carry flag, Sign flag, zero flag, minus one flag and an IRQ enable flag. The carry and minus one flags always comes off the output of the ALU, while the sign flag comes off bit 15 of the ALU function result, and zero flag as previously mentioned. The IRQ enable flag is used to prevent interrupt requests from hardware from interrupting the processor; this flag is cleared on reset.
74LS612 Memory Mapper & System Boot Flip-Flop
This memory mapper chip has 16 internal registers of 12 bits each, and divide the 16-bit system memory map up into 16x 4 kilobyte banks that may map any RAM, ROM, or system I/O resources as the system sees fit. Moreover, the memory mapper expands the system’s addressing capabilities up to 5 mega bytes when configured for using the direct decode mode, and up to 32 MB when additional decoders are used by system expansion hardware. On reset, the memory mapper is disabled, and needs to be programmed before any other system resources become available. A one-clock CPU wait state is generated when writing to the LS612 registers to insert a full-cycle strobe pulse within a 2-cycle period to satisfy the LS612 timing requirements.
Boot Mode Jumpers
Before programming the LS612 memory mapper chip after reset, the boot mode jumpers select the default memory to be used to boot the system. In general, this should be set to ROM BIOS memory, although RAM and expansion I/O can be selected as well. If no memory device is selected for boot at all, the system will use the 16 front panel switches as the boot memory; this experimental setting is only useful in the single-step DC clocking mode for atomically feeding the CPU instructions one 16-bit word at-a-time.
5-bit Direct Decode Control Bus
To use the direct decode function of the system memory mapper, the most significant 5 bits of the map data decode to RAM, ROM, or I/O resources directly by clearing one of these bits, while keeping the rest at logic level 1.
19-bit Address Bus
Each direct decode resource has its own 19-bit address space; with a 16-bit bus, this equates to 1 MB.
16-bit Data Bus
The system has a 16-bit data path directly coupled with the A, B, flags and opcode register, memory mapper and IRQ priority registers, as well as with the expansion headers.
8 System Expansion Headers
Each expansion header has access to a 19-bit address bus, 5-bit direct decode bus, 16-bit data bus, non-maskable and discrete IRQ inputs, system wait line, read/write control and propagation-matched memory clocking lines. The IRQ priority designation here is a function of the expansion header used by the hardware making the interrupt request.
16 Console Pushbutton Switches
These mechanical toggle switches can be mapped into the CPU by setting all 12 bits of a memory mapper register to logic level 1.
4 System Control Pushbutton Switches
These system configuration switches control the CPU reset input, manual NMI trigger, single-step and variable clock speed modes as well as the 12 MHz full-speed mode.
Interrupt Microprogram Fetch Sequencer
Whenever an interrupt request, non-maskable interrupt, or breakpoint instruction is executed, the processor stops what it is doing in the main program and executes a microprogram which pushes the B, Flags, PC, and A registers to the stack, while fetching the system call vector at $FFFF. From the system call, the IRQ priority can be analyzed by reading from the memory mapper port to determine the level of the IRQ (if any), or whether an NMI or breakpoint occurred.
The breakpoint and NMI/IRQ will push the flags to the stack first, and then clear the IRQ enable flag. When the enable is clear, the IRQ input lines are all latched until the flags register is written to again with the IRQ enable flag set, typically done in the return from interrupt code sequence. Any pending IRQs will be processed after the return from interrupt sequence, while a NMI can be triggered at any time with a negative edge line transition on the NMI open-drain input.
Instruction Word Register
Instruction words are 16-bits each, and take just 2 clock cycles to execute (though instructions writing to the 74LS612 registers take 3 cycles). They are organized as a 4-bit buscode, 1-bit carry mode and 3-bit operand select, 5-bit ALU function code and 3-bit address register select (the A input of the ALU) bitfields. The bus codes are responsible for establishing the data bus path and instruction mode of the CPU. The ALU flags are only updated when using certain bus codes, while the IRQ enable flag can only be updated when loading the flags register from memory. Note that an extra optional chip is present here for increasing the line current for ALU function lines 0 to 3 when using the AS881 ALUs.
Instruction Decoders
The 74F139 and 74F154 chips are used to mostly decode the bus modes of the CPU and provide the discrete control lines used to switch different parts of the CPU on and off. Moreover, the 74F538 parts are used to decode the CPU register to update with the ALU result of the instruction.
Multiply & Divide Instruction Slices
The processor has 2 specific instruction types for performing an iterative 16-bit multiply or divide calculation, using inlined instructions. Moreover, the division and multiplication functions are a subset of the conditional store instruction group, where the execute cycle will determine the condition to store the result of the ALU to the B register, and subsequently shift the B and R7 registers accordingly, while simultaneously fetching the next instruction opcode. This allows a 16-bit calculation to be done using 16 back-to-back MUL or DIV instructions, and some setup code that may cascade multiple 16-bit MUL or DIV results together for multi-word calculations.
208 Console Status LEDs
In the single-step clocking and variable-speed clock mode, these front panel LEDs provide the status of virtually every relevant bit line in the computer, for the aid of programming, debugging, learning, or just providing an entertaining LED display for others to casually enjoy as a background showpiece.
Conclusion
In this guide we covered the basic architecture of the 74LS181/AS881 16-bit TTL computer.
Based on the reception of this project, it may be followed up with a PCB design for the computer, then with actually building and testing it, and releasing the project with a complete bill of materials on GitHub.
