USB-NES employs a standardized method of testing and identifying dozens of simple types of common NES and Famicom cartridge boardsets using 74LS161 logic chips or similar hardware, via its BCMTABLE.BIN interface and internal testing engine described in detail here.
Bus Contention Mapper Theory
The philosophy is that you have one single 8-bit bankswitch register mapped into the PRG-ROM memory @ $8000-$FFFF for both the PRG-ROM and CHR-ROM, as well as bits for possible meddling with PPU mirroring. The bits to do these 3 things can be in any order, and the PRG and CHR fields can have any size too. Combinations of the absence of these attributes are also a thing. Also the PRG-ROM is enabled on writes to the mapper, so it is necessary for the ROM to already contain the data value you wish to program the register with.
Probability with Bus Contention Mappers
Because of the PRG-ROM bus contention situation on mapper write cycles, we are compelled to either not interfere with the PRG data bus at all, or to match the value of the ROM data while driving the bus in parallel on a simulated CPU write cycle. Either way, the richness of the ROM data determines what is possible as far as being able to build a complete bankswitch data table or not, because no other values are allowed to be written as these would cause a bus contention situation and make the hardware throw a fit.
Zero is the most common data byte type, and therefore to switch the mapper into the root bank for the first time, USB-NES simply scans the PRG-ROM space until a zero is encountered and then writes a zero to the mapper at that address. Once in the root bank, the entire PRG-ROM space in $8000 – $FFFF is profiled to discover and record the addresses of data values 0 to 255.
If the data table table can not be completed properly due to sparse ROM data, then it is possible for the USB-NES auto-detection system to incorrectly identify the boardset or even not at all.
Enable the BCMTABLE reporting files
Set the BCMTABLE_reporting setting to 1 in SETTINGS.TXT to enable showing the DATA_TBL.BIN, ROOT_TBL.BIN and BCMSCORE.BIN files on the USB-NES drive.
DATA_TBL.BIN file
The data table is a 256 entry list of 16-bit addresses in the PRG-ROM where data bus values for numbers 0 to 255 were discovered in the root bank.
ROOT_TBL.BIN file
The root table is a 256 entry list of 16-bit addresses in the PRG-ROM area where 0x00 data values were discovered in banks 0 to 255.
BCMSCORE.BIN file
The simplest way to describe the auto-detection system USB-NES uses to identify a bus-contention boardset mapper type is to try values 0 thru 255 on the mapper to see which banks in the PRG-ROM and CHR-ROM space are affected, and/or whether any changes are detected on the CIRAM_A10 line. When changes are detected, the bankswitch bits causing the activity are flagged in appropriate sections of the BCMSCORE.BIN table to indicate the overall personality of the mapper.
Matching the BCMSCORE profile to a BCMTABLE descriptor
Once the BCMSCORE is calculated, the set bits in byte locations 0x03 – 0x0F are matched up against bytes 0x03 – 0x0F of each descriptor in BCMTABLE.BIN. From this range, at least one bit from every byte in in the BCMSCORE must match any bits set in the BCMTABLE descriptor bytes (and no where else) for the mapper to be considered a possible candidate for selection, otherwise it is rejected and the next descriptor is tested until the end of list.
In the uncommon case where the BCMSCORE is able to be matched to more than one simultaneous descriptor in the BCMTABLE.BIN, USB-NES employs a second discrimination system here that is based on favouring the mapper descriptor capable of creating the largest1 .NES ROM file among the candidates.
- Except in a very rare case of potential CPROM boardset mapper 13 detection.
Enable the BCMTABLE.BIN file
Set the BCMTABLE.BIN_enable setting to 1 in SETTINGS.TXT to enable showing the BCMTABLE.BIN file on the USB-NES drive.
BCMTABLE.BIN Descriptor Type
The BCMTABLE.BIN file contains up to 32 BCM descriptors of 32 bytes each (1 KB max.), and each descriptor slot can describe one simple mapper type.
| Offset | Size | Description |
|---|---|---|
| 0x00 | 1 | Mapper number 0: list terminator 1 – 255: valid descriptor |
| 0x01 | 1 | Bankswitching configuration cccc PPqq qq: PRG-ROM bank offset (00: $8000; 01: $A000; 10: $C000; 11: $E000) PP: PRG-ROM bank size (00: 32 KB; 01: 16 KB; 10: undefined; 11: 8 KB) cccc: CHR-ROM bank size and offset 0000: bank size = 0 KB (CHR-RAM pres.) 0001: bank size = 8 KB; offset = $0000 001x: bank size = 4 KB; offset = x << 12 01xx: bank size = 2 KB; offset = xx << 11 1xxx: bank size = 1 KB; offset = xxx << 10 |
| 0x02 | 1 | Reserved (set to 0) |
| 0x03 | 1 | Mirroring control bitmap |
| 0x04 | 1 | PRG $8000 – $9FFF bankswitch bitmap |
| 0x05 | 1 | PRG $A000 – $BFFF bankswitch bitmap |
| 0x06 | 1 | PRG $C000 – $DFFF bankswitch bitmap |
| 0x07 | 1 | PRG $E000 – $FFFF bankswitch bitmap |
| 0x08 | 1 | CHR $0000 – $03FF bankswitch bitmap |
| 0x09 | 1 | CHR $0400 – $07FF bankswitch bitmap |
| 0x0A | 1 | CHR $0800 – $0BFF bankswitch bitmap |
| 0x0B | 1 | CHR $0C00 – $0FFF bankswitch bitmap |
| 0x0C | 1 | CHR $1000 – $13FF bankswitch bitmap |
| 0x0D | 1 | CHR $1400 – $17FF bankswitch bitmap |
| 0x0E | 1 | CHR $1800 – $1BFF bankswitch bitmap |
| 0x0F | 1 | CHR $1C00 – $1FFF bankswitch bitmap |
| 0x10 | 16 | Mapper text description |
| 0x20 |