This section shows off photography from miscellaneous NES and Famicom boardset hardware, brief hardware rundown and notes on USB-NES compatibility if any.
Yeah Yeah Beebiss II
Yeah Yeah Beebiss II is a fun and easy to pick-up-n-play co-op, arcade style game for NES; now officially supported on USB-NES with firmware version 0.79 or later.
UNROM 512 + Save RAM
Alwa’s awakening is an interesting boardset because it combines UNROM type with 8 KB battery-backed save RAM @ PRG $6000.
USB-NES identifies this boardset internally as mapper 30, but mapper 30 generally uses PRG-flash instead of battery-backed save RAM and so it is a better solution to represent this boardset as mapper type 2 and set the battery flag attribute in the .NES header of the game image.
Currently there are some emulators that will not support this type of boardset. Specifically, these emulators seem to not allow the simultaneous use case of UNROM with any battery save RAM, even though in practice these two resources can be combined rather easily.
Writing to save RAM on this boardset is enabled right after power-up; it is unknown if a hardware register exists someplace that may control the write-protect for it.
Alwa’s Awakening is compatible with USB-NES firmware v0.75 or later, and can be played on NEStopia v1.4 or later.
The Maxi 15-in-1 is one of the most iconic NES multicarts released back in the day. Besides being one of the rare legal multicarts around, it has a number of decent games on it, most of which are puzzle-oriented and fascinating enough to provide many hours of entertainment.
The Maxi 15 implements an interesting copy protection system that only allows the outer bankswitch register to be programmed once after reset, thus making reading out the entirety of the ROMs over the NES bus interface particularly difficult1 on one try.
When line CPU A0 (cart pin 13) is driven high, it charges a 0.1 uF capacitor up through a series diode and 1K ohm resistor2, and this signal is buffered through two daisy-chained 74HC04 inverters to drive the active-low reset inputs3 on both the inner and outer bankswitch registers. There is a 100 K ohm discharge resistor across the capacitor, which equates to an RC time constant of about 10 milliseconds.
The boardset then determines the NES reset state by detecting a persistent low logic level or float condition on CPU address line A0, which only happens when the 2A03 CPU is under reset4.
When bits D0 – D5 are written to the outer bankswitch register @ $FF80-$FF9F with a 1 in any of these bits, it locks up the outer bankswitch register value until reset is detected. Therefore, to read out the entire ROM contents in this cart sequentially, it is necessary to time out the discharge time of the RC circuit between outer bankswitching reg changes, while keeping the CPU A0 line driven to a low logic level or in a high-impedance state.
Bank 0 is actually the most difficult PRG ROM bank to read out in proper sequential fashion since under normal circumstances5,6,7, any access to PRG ROM data @ $FF80-$FF9F will cause an unwanted bankswitch away from bank 0.
Moreover, the values in ROM bank 0 @ $FF80-$FF9F dictate what banks can be accessed, and bank 15 is not even directly accessible8 from the outer bankswitch register because the value is not present in the Maxi 15 ROM outer bankswitch table.
The Maxi 15 boardset is now supported on USB-NES with firmware v0.75 or later.
- This is likely impossible to do on an unmodified NES/Famicom, without the user being prompted by a dedicated cart dumping program to manually press reset on the console 15 times or so to read out every individual bank that way.
- Refer to the diode + RC combo circuit just above the left-side CHR-ROM in the topside boardset pic above.
- The high logic level threshold on CPU A0 to charge the capacitor and subsequently negate the bankswitch register reset lines through the two 74HC04 inverters here is about 3.0 volts.
- Outside of reset, there is no known way to run an NES/Famicom with software that can hold the CPU A0 line at a low logic level long enough to discharge the capacitor and subsequently reset the bankswitch registers here.
- Immediately after power-up/reset, or otherwise from the point that the capacitor has been completely discharged, it is possible to read out the data @ PRG $FF80-$FF9F in bank 0 without inadvertently triggering a bankswitch, if the data is read out very quickly before the capacitor is able to charge back up to the level required to negate the reset line on the bankswitch register.
- Only odd address access to the bankswitch registers @ PRG $FF80-$FF9F charge the capacitor.
- This may be impossible with the cartridge running on an actual NES/Famicom console.
- Accessing bank 15 involves setting the outer bankswitch register for bank 14 and subsequently after the bankswitch, using the inner PRG bankswitch table @ $FFE8 to access bank 15.
NES Mother Repro
As of firmware v0.75, USB-NES supports this boardset as “NES 240”; basically an MMC3 clone that uses a boot loader to load 256 KB of graphics data from the first half of the PRG ROM into CHR-RAM.
USB-NES transparently handles the redirection of CHR-ROM data to the PRG-ROM in this case to create a .NES file image that resembles a typical MMC3 boardset type. The game itself relies on ROM-based CHR graphics to work properly, and the boot loader has no functional relationship with the game other than to load the CHR-RAM with graphics and then make it read-only.
The initialization sequences of this game write 0x00 to both $5000 and $5100 registers, and after that it goes into 512KB PRG : 256 CHR MMC3 mode and the bootloader goes invisible. Currently, the only known way to swap back in the bootloader page is to power-cycle the game boardset.
Data East All Star Collection
Despite the questionable choice for Retro-Bit to use a non-standard cartridge shell for their DE Collection game, this is actually a pretty cool game to have when throwing parties because all six games on here are easy to learn pick-up-n-play games that go well with friends and good times.
Kira Kira Star Night DX
Acclaim’s MC-ACC (MMC3 Clone)
The MC-ACC is basically an MMC3 clone with one notable exception: it uses the /ROMSEL line to determine the CPU A15 status at the end of the CPU clock cycle (M2), as opposed to just using /ROMSEL itself to do the MMC3 register clocking. Thus, proper emulation of the NES/Famicom’s CPU address decoder logic delay (about 15 nanoseconds) for /ROMSEL is necessary to properly program the MMC3 registers here.